The present invention relates to electronic circuits, and more particularly, to level shifter circuits and methods.
Input/output (IO) buffers in many field programmable gate array (FPGA) devices receive charge from a 2.5 volt supply voltage. The IO buffers in these FPGA devices have 2.5 volt transistors that are used to support legacy IO standards such as low voltage transistor—transistor logic (LVTTL) and Peripheral Component Interconnect (PCI). Transistors in the core area of an FPGA device receive charge from a low supply voltage. When an input signal from the core of the FPGA that varies between ground (at 0 volts) and the low supply voltage reaches the 10 buffer, the input signal is level shifted to an output signal that varies between a supply voltage of 2.5 volts and ground.
FIG. 1 illustrates a conventional level shifter circuit 100. Level shifter circuit 100 can generate an output signal OUT having a frequency up to 333 Megahertz (MHz). Level shifter 100 includes p-channel metal oxide semiconductor (MOS) field-effect transistors 101-102, n-channel MOS field-effect transistors 103-104, and inverters 105-106. An input signal IN is transmitted to an input of level shifter circuit 100 from the core circuitry of an FPGA integrated circuit. The core circuitry of the FPGA is powered by a low supply voltage VCC. Inverters 105-106 also receive supply voltage VCC. The sources of transistors 101-102 are coupled to a supply voltage node at a high supply voltage VCCIO.
When input signal IN is in a logic low state, transistor 103 is off, transistor 104 is on, transistor 101 is on, and transistor 102 is off, and level shifter 100 drives output signal OUT to a logic low state (i.e., at the ground voltage). When input signal IN is at VCC (i.e., in a logic high state), transistor 103 is on, transistor 104 is off, transistor 101 is off, and transistor 102 is on, and level shifter 100 drives output signal OUT to supply voltage VCCIO. Transistors 101-104 are thick oxide devices that have threshold voltages of about 0.6 volts.
If VCC equals 0.85 volts, and VCCIO equals 2.5 volts, the gate-source voltage overdrive for PMOS transistors 101-102 is 2.5 volts−0.6 volts=1.9 volts, and the gate-source voltage overdrive for NMOS transistors 103-104 is 0.85 volts−0.6 volts=0.25 volts. Because the gate-source voltage overdrive for PMOS transistors 101-102 is much larger than the gate-source voltage overdrive for NMOS transistors 103-104, NMOS transistors 103-104 are designed to have much larger width-to-length channel ratios than PMOS transistors 101-102. Because transistors 103-104 have a low gate-source voltage overdrive, the speed of level shifter 100 is sensitive to variations in the supply voltage VCC and the threshold voltages of transistors 101-104.
Another disadvantage of level shifter 100 is that capacitive coupling between the input node at INB and the output node at OUT slows down the transition of the output signal OUT. For example, in order for output signal OUT to transition from 0 volts to VCCIO, a low-to-high transition in input signal IN needs to propagate through inverters 105-106 and transistor 103 to turn on transistor 102. The low-to-high transition in input signal IN also propagates through inverter 105 to turn off transistor 104. Because the delay path through inverter 105 and transistor 104 is shorter, a high-to-low transition in signal INB couples negative charge to output signal OUT, causing OUT to dip before transistor 102 pulls OUT to VCCIO, which slows down the rising edge in output signal OUT.
FIG. 2 illustrates a prior art level shifter circuit 200 that can generate an output signal OUT having a frequency of up to 600 MHz. Level shifter circuit 200 includes PMOS field-effect transistors 201-204, NMOS field-effect transistors 205-208, and inverters 209-210. NMOS transistors 205-206 are native NMOS transistors that have threshold voltages of about zero volts. Transistors 207-208 are thin oxide transistors that have threshold voltages of about 0.25 volts. Transistors 201-206 are thick oxide transistors. The transistors in inverters 209-210 are thin oxide transistors.
If VCC is 0.85 volts, and VCCIO is 2.5 volts, the pull down gate-source overdrive voltage of transistors 207-208 is increased compared to level shifter 100 to 0.85 volts−0.25 volts=0.6 volts. Although transistors 205-206 have threshold voltages near zero volts, transistor 207 is off when transistor 208 is on preventing leakage current through transistor 207, and transistor 208 is off when transistor 207 is on preventing leakage current through transistor 208. Native NMOS transistors 205-206 isolate thin oxide transistors 207-208 so that transistors 207-208 are not exposed to an over stress of 2.5 volts from VCCIO.
One disadvantage of level shifter circuit 200 is that by coupling transistors 202 and 204 in series, the pull up current to the output signal OUT is reduced, which reduces the maximum frequency of OUT. Another disadvantage of level shifter circuit 200 is that the addition of transistor 204 increases capacitive coupling between the node at INB on the gates of transistors 204 and 206 and the output node at OUT.